The present invention relates generally to integrated circuit routing, and more particularly to a method and system for gathering and displaying pin congestion statistics using a graphical user interface.
Integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The physical design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
The objective of physical design is to determine an optimal arrangement of devices in a plane or in a three dimensional space, and an efficient interconnection or routing scheme between the devices to obtain the desired functionality. Since space on a wafer is very expensive real estate, algorithms must use the space very efficiently to lower costs and improve yield.
The input to the physical design problem is a circuit diagram, and the output is the layout of the circuit. The physical design is accomplished in several stages including partitioning, floor-planning, placement, and routing.
A chip may contain several million transistors. Layout of the entire circuit cannot typically be handled by currently available floor-planning tools due to the limitation of memory space as well as the computational power available. Therefore, the circuit is normally partitioned by grouping the components into functional blocks such as subcircuits and modules. The actual partitioning process considers many factors such as the size of the blocks, number of blocks and number of interconnections between the blocks.
The output of partitioning is a set of blocks, along with the interconnections required within and between blocks. The set of interconnections required is referred to as a netlist. In large circuits, the partitioning process is often hierarchical, although non-hierarchical (e.g. flat) processes can be used, and at the topmost level a circuit typically has between 5 to 25 blocks. However, greater numbers of blocks are possible and contemplated. Each block is then partitioned recursively into smaller blocks.
The floor-planning step is concerned with selecting good layout alternatives for each block of the entire chip, as well as between blocks and to the edges. Floor-planning is a critical step as it sets up the ground work for a good layout. However it is computationally quite hard. Very often the task of floorplan layout is done by a design engineer using a CAD tool. This is necessary as the major components of an IC are often intended for specific locations on the chip.
During placement, the blocks and locations of the block terminals, referred to hereinafter as block “pins”, within the blocks are exactly positioned on the chip. The goal of placement is to find a minimum area arrangement for the blocks that allows completion of interconnections defined by the netlist. Placement is typically done in two phases. In the first phase, an initial placement is created. In the second phase, the initial placement is evaluated and iterative improvements are made until the layout has minimum area and conforms to design specifications.
During the physical design of an integrated circuit, un-foreseen routing congestion issues can arise when the floor-planning process does not address the full details involved in fully implementing the physical realization of the blocks and the interconnects between them. Often times, the design database is somewhat simplified or not yet complete in the floor-planning application. An example of one such simplification is the existence of pins defined on the edges of blocks which do not have associated net connectivity within or outside of the block. When determining and analyzing the placement of such pins, the floor-planning application and the integrated circuit designer have no insight into the additional routing congestion which will be realized when the additional connectivity is added at a later time. This can cause routing congestion problems both inside of the block and at the top-level.
In the past, the quality of block and block pin placement could not be determined until the routing phase had been completed. Due to the complexity of the routing problem, it is well known that a particular block placement may lead to an unroutable design. For example, routing may not be possible in the space provided. However, given an unroutable placement design, it is often the case that the source of the unroutablility problem lies in routing congestion around the block pins. Accordingly, often an otherwise unroutable block placement design may be made routable by changing the placement of the block pins within the blocks.
However, because there does not currently exist any automated solution of collecting, determining, and displaying pin placement congestion statistics, integrated circuit designers must wait for completion of routing to determine the routability/unroutability and quality of a given integrated circuit floorplan. Because the analysis of the congestion is done post-route, needless wasted time is often spent trying to route to pins that are arranged such that routing to them is virtually impossible or at least requires a lot of manual steps to fix.
It would therefore be desirable to have a method for collecting and analyzing pin congestion statistics to allow replacement of block pins prior to performing inter-block routing in integrated circuits.